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syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 1 product list SM5964C25, 25mhz 64kb internal flash mcu sm5964c40, 40mhz 64kb internal flash mcu description the sm5964 series product is an 8 - bit single chip micro controller with 64kb flash & 1k byte ram embedded. it has in-system programming (isp) function and is a derivative of the 8052 micro controller family. it has 5-channel spwm build-in. with its hardware features and powerf ul instruction set, it?s straight forward to make it a versatile and cost effective controller for those applications which demand up to 32 i/o pins for pdip package or up to 36 i/o pins for plcc/qfp package, or applications which need up to 64k byte flash memory either for program or for data or mixed. to program the on-chip flash memory, a commercial writer is available to do it in parallel programming method. the on-chip flash memory can be programmed in either parallel or serial interface with its isp feature. ordering information yymmv sm5964ihhkl yy: year, ww: month v: version identifier{ , a, b,?} i: process identif ier {l=3.0v~3.6v,c=4.5v~ 5.5v} hh: working clock in mhz {25, 40} k: package type postfix {as below table} l:pb free identifier {no text is non-pb free p is pb free} postfix package pin / pad configuration dimension p 40l pdip page 2 page 23 j 44l plcc page 2 page 24 q 44l qfp page 2 page 25 features z working voltage:4.5v through 5.5v z general 8052 family compatible z 12 clocks per machine cycle z 64k byte on chip program flash with in-system programming(isp) capability z 1024 bytes on chip data ram z three 16 bit timers/counters z one watch dog timer z four 8-bit i/o ports for pdip package z four 8-bit i/o ports + one 4-bit i/o ports for plcc or qfp package z full duplex serial channel z bit operation instruction z industrial level z 8-bit unsigned division z 8-bit unsigned multiply z bcd arithmetic z direct addressing z indirect addressing z nested interrupt z two priority level interrupt z a serial i/o port z power save modes: idle mode and power down mode z code protection function z low emi (inhibit ale) z reset with address $000 0 blank initiate isp service program z isp service program space configurable in n*512 byte (n=0 to 8) size z five channel specific pwm(spwm) build-in with p1.3~p1.7 taiwan 6f, no.10-2 li- hsin 1st road , science-based industrial park, hsinchu, taiwan 30078 tel: 886-3-567-1820 886-3-567-1880 fax: 886-3-567-1891 886-3-567-1894
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 2 pin configuration
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 3 block diagram
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 4 pin description 40l pdip pin# 44l qfp pin# 44l plcc pin# symbol active i/o names 1 40 2 p1.0/t2 i/o bit 0 of port 1 & timer 2 clock out 2 41 3 p1.1/t2ex i/o bit 1 of port 1 & timer 2 control 3 42 4 p1.2 i/o bit 2 of port 1 4 43 5 p1.3/spwm0 i/o bit 3 of port 1 & spwm channel 0 5 44 6 p1.4/spwm1 i/o bit 4 of port 1 & spwm channel 1 6 1 7 p1.5/spwm2 i/o bit 5 of port 1 & spwm channel 2 7 2 8 p1.6/spwm3 i/o bit 6 of port 1 & spwm channel 3 8 3 9 p1.7/spwm4 i/o bit 7 of port 1 & spwm channel 4 9 4 10 res h i reset 10 5 11 p3.0/rxd i/o bit 0 of port 3 & receiver data 11 7 13 p3.1/txd i/o bit 1 of port 3 & transmit data 12 8 14 p3.2/#int0 l/- i/o bit 2 of port 3 & low true interrupt 0 13 9 15 p3.3/#int1 l/- i/o bit 3 of port 3 & low true interrupt 1 14 10 16 p3.4/t0 i/o bit 4 of port 3 & timer 0 15 11 17 p3.5/t1 i/o bit 5 of port 3 & timer 1 16 12 18 p3.6/#wr i/o bit 6 of port 3 & ext. memory write 17 13 19 p3.7/#rd i/o bit 7 of port 3 & ext. memory read 18 14 20 xtal2 o crystal out 19 15 21 xtal1 i crystal in 20 16 22 vss sink voltage, ground 21 18 24 p2.0/a8 i/o bit 0 of port 2 & bit 8 of ext. memory address 22 19 25 p2.1/a9 i/o bit 1 of port 2 & bit 9 of ext. memory address 23 20 26 p2.2/a10 i/o bit 2 of port 2 & bit 10 of ext. memory address 24 21 27 p2.3/a11 i/o bit 3 of port 2 & bit 11 of ext. memory address 25 22 28 p2.4/a12 i/o bit 4 of port 2 & bit 12 of ext. memory address 26 23 29 p2.5/a13 i/o bit 5 of port 2 & bit 13 of ext. memory address 27 24 30 p2.6/a14 i/o bit 6 of port 2 & bit 14 of ext. memory address 28 25 31 p2.7/a15 i/o bit 7 of port 2 & bit 15 of ext. memory address 29 26 32 #psen l o program storage enable 30 27 33 ale - o address latch enable 31 29 35 #ea l i external access 32 30 36 p0.7/ad7 i/o bit 7 of port 0 & data/address bit 7 of ext. memory 33 31 37 p0.6/ad6 i/o bit 6 of port 0 & data/address bit 6 of ext. memory 34 32 38 p0.5/ad5 i/o bit 5 of port 0 & data/address bit 5 of ext. memory 35 33 39 p0.4/ad4 i/o bit 4 of port 0 & data/address bit 4 of ext. memory 36 34 40 p0.3/ad3 i/o bit 3 of port 0 & data/address bit 3 of ext. memory 37 35 41 p0.2/ad2 i/o bit 2 of port 0 & data/address bit 2 of ext. memory 38 36 42 p0.1/ad1 i/o bit 1 of port 0 & data/address bit 1 of ext. memory 39 37 43 p0.0/ad0 i/o bit 0 of port 0 & data/address bit 0 of ext. memory 40 38 44 vdd drive voltage 17 23 p4.0 i/o bit 0 of port 4 28 34 p4.1 i/o bit 1 of port 4 39 1 p4.2 i/o bit 2 of port 4 6 12 p4.3 i/o bit 3 of port 4
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 5 special function register (sfr) the address $80 to $ff can be access ed by direct addressing mode only. address $80 to $ff is sfr area. the following table lists the sfrs which are identical to general 8052 as well as sm5964 extension sfrs . special function register (sfr) memory map $f8 $ff $f0 b ispfah ispfal ispfd ispc $f7 $e8 $ef $e0 acc $e7 $d8 p4 $df $d0 psw $d7 $c8 t2con t2mod rcap2l rcap2h tl2 th2 $cf $c0 $c7 $b8 ip sconf $bf $b0 p3 $b7 $a8 ie spwmd4 $af $a0 p2 spwmc spwmd0 spwmd1 spwmd2 spwmd3 $a7 $98 scon sbuf p1con wdtc $9f $90 p1 $97 $88 tcon tmod tl0 tl1 th0 th1 $8f $80 p0 sp dpl dph rcon pcon $87 note: the text of sfrs with bold type characters are extension sp ecial function registers for sm5964 addr sfr reset 7 6 5 4 3 2 1 0 85h rcon ******00 rams1 rams0 9bh p1con 00000*** spwm4e spwm3e spwm2 e spwm1e spwm0e 9fh wdtc 0*0**000 wdte reserved** clear ps2 ps1 ps0 a3h spwmc ******00 pdiv1 pdiv0 a4h spwmd0 00h spwmd04 spwmd03 spwmd02 spwmd01 spwmd00 brm02 brm01 brm00 a5h spwmd1 00h spwmd14 spwmd13 spwmd12 spwmd11 spwmd10 brm12 brm11 brm10 a6h spwmd2 00h spwmd24 spwmd23 spwmd22 spwmd21 spwmd20 brm22 brm21 brm20 a7h spwmd3 00h spwmd34 spwmd33 spwmd32 spwmd31 spwmd30 brm32 brm31 brm30 ach spwmd4 00h spwmd44 spwmd43 spwmd42 spwmd41 spwmd40 brm42 brm41 brm40 bfh sconf 0****010 wdr ispe ome alei c9h t2mod ******00 * * * * * * t2oe dcen d8h p4 ****1111 p4.3 p4.2 p4.1 p4.0 f4h ispfah 00h fa15 fa14 fa13 fa12 fa11 fa10 fa9 fa8 f5h ispfal 00h fa7 fa6 fa5 fa4 fa3 fa2 fa1 fa0 f6h ispfd 00h fd7 fd6 fd5 fd4 fd3 fd2 fd1 fd0 f7h ispc 0*****00 start f1 f0 ** keep to ?0? when write wdtc (9fh).
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 6 extension function description 1. memory structure the sm5964 is the general 8052 hardware core to integrate the isp function as a single chip micro controller. it?s memory structure follows general 8052 structure . 1.1 program memory the sm5964 has 64k byte on-chip flash memory which us ed as general program memory, on which include up to 4k byte specific isp service program me mory space. the address range for the 64k byte is $0000 to $ffff. the address range for the isp service program is $f000 to $ffff. the i sp service program size can be partitioned as n blocks of 512 byte (n=0 to 8). when n=0 means no isp service prog ram space available, total 64k byte memory used as program memory. when n=1 means memory address $fe00 to $ffff reserved for isp service program. when n=2 means memory address $fc00 to ffff re served for isp service program,...etc . value n can be set and programmed into sm5964 by writer. 1.1.1 program code security movc instruction executed from external program memory space will not be ab le to fetch internal codes from on chip program memory after the chip is protected on the writer. .
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 7 1.2 data memory the sm5964 has 1k bytes on-chip ram, 256 bytes of it are the same as genera l 8052 internal memory structure while the expanded 768 bytes on-chip ram can be accessed by external memory addressing method (by instruction movx.). 1.2.1 data memory - lowe r 128 byte ($00 to $7f) data memory $00 to $ff is the same as 8052. the address $00 to $7f can be accessed by direct and indirect addressing modes. address $00 to $1f is register area. address $20 to $2f is memory bit area. address $30 to $7f is for general memory area. 1.2.2 data memory - higher 128 byte ($80 to $ff) the address $80 to $ff can be accessed by indirect addressing mode . address $80 to $ff is data area. 1.2.3 data memory - expanded 768 bytes ($0000 to $02ff) from external address $0000 to $02ff is the on-chip expanded ram area, total 768 bytes. this area can be accessed by external direct addressi ng mode (by instruction movx). if the address of instruction movx @dptr is larger t han $02ff then sm5964 will generate the external memory control signal automatically. the bit 1 (ome) of special function register $bf (sconf) can enable or disable this expanded 768 byte ram. the default setting of ome bit is 1 (enable).
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 8 1.3 system control register (sconf, $bf) bit-7 bit-0 wdr unused unused unus ed dfen ispe ome alei read / write: r/w - - - - r/w r/w r/w reset value: 0 * * * * 0 1 0 wdr: watch dog timer reset. when system reset by watch dog timer overflow, wdr will be set to 1. ispe: isp function enable bit ome: 768 bytes on-chip ram enable bit . alei: ale output inhibit bit, to reduce emi . setting bit 0 (alei) of sconf can inhibit the clock signal in fosc/6hz output to the ale pin. the bit 1 (ome) of sconf can enable or disable the on-chip expanded 768 byte ram. the default setting of ome bit is 1 (enable). the bit 7 (wdr) of sconf is watch dog timer reset bit. it will be set to 1 when reset signal generated by wdt overflow. user should check wdr bit whenever un-predicted reset happened. 2. port 4 for plcc or qfp package: the bit addressable port 4 is available with plcc or qf p package. the port 4 has only 4 pins and its port address is located at 0d8h. the function of port 4 is the sa me as the function of port 1, port 2 and port 3. port4 (p4, $d8) bit-7 bit-0 unused unused unused unused p4.3 p4.2 p4.1 p4.0 read / write: - - - - r/w r/w r/w r/w reset value: * * * * 1 1 1 1 the bit 3, bit 2, bit 1, bit 0 output the setting to pin p4.3, p4.2, p4.1, p4.0 respectively.
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 9 3. in-system programming (isp) function the sm5964 can generate flash control signal by internal hardware circuit. us er utilize flash control register, flash address register and flash data register to perform the isp function wit hout removing the sm5964 from the system. the sm5964 provides internal flash control signals whic h can do flash program/chip erase/page erase/protect functions. user need to design and use any kind of inte rface which sm5964 can input data. user then utilize isp service program to perform the flash program /chip erase/page erase/protect functions. 3.1 isp service program the isp service program is a user developed firmware progra m which resides in the isp se rvice program space. after user developed the isp service program, user then determi ne the size of the isp service program. user need to program the isp service program in the sm5964 for the isp purpose. the isp service program were developed by user so that it should includes any features which relates to the flash memory programming function as well as communication protocol between sm5964 and ho st device which output data to the sm5964. for example, if user utilize uart interf ace to receive/transmit data between sm5964 and host device, the isp service program should include baud rate, checksum or parity check or any error-checking mechanism to avoid data transmission error. the isp service program can be initiated under sm5964 active or idle mode. it can not be initiated under power down mode. 3.2 lock bit (n) the lock bit n has two functions: one is for service program si ze configuration and the other is to lock the isp service program space from flash erase function. the isp service program space address range from $f000 to $ffff. it can be divided as blocks of n*512 byte. (n=0 to 8). when n=0 means no isp function, all of 64k byte flash memory can be used as program memory. when n=1 means isp service program occupies 512 byte while the re st of 63.5k byte flash memory can be used as program memory. the maximum isp service progra m allowed is 4k byte for n=8. unde r such configuration, the usable program memory space is 60k byte. after n determined, sm5964 will reserve the isp service pr ogram space downward from the top of the program address $ffff. the start addres s of the isp service program located at $fx00 while x is an even number, depending on the lock bit n. please see page 7 program memory diagr am for this isp service program space structure.
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 10 the lock bit n function is different from the flash protect function. the flash er ase function can erase all of the flash memory except for the locked isp service program space. if the flash not been protected, the content of isp service program still can be read. if the flash been protected, the overall co ntent of flash program memory space including isp service program space can not be read. 3.3 program the isp service program after lock bit n is set and isp service program been progra mmed, the isp service program memory will be protected (locked) automatically. the lock bit n has its own progra m/erase timing. it is different from the flash memory program/erase timing so the locked isp service program ca n not be erased by flash erase function. if user need to erase the locked isp service program, he can do it by writ er only. user can not change isp service program when sm5964 was in system. 3.4 initiate isp service program to initiate the isp service program is to load the progra m counter (pc) with start addr ess of isp service program and execute it. there are three ways to do so: (1) blank reset. hardware reset with first flash address blank ($0000=#ffh) will load the pc with start address of isp service program. (2) execute ?jump? instruction can load the star t address of the isp service program to pc. user can initiate general 8052 int function to initiate the isp service program. after i sp service program executed, user need to reset the sm5964, either by hardware reset or by wdt, or jump to the address $0000 to re-start the firmware program. isp registers - ispfah, ispfal, ispfd and ispc isp flash address-high register(ispfah,$f4) bit-7 bit-0 fa15 fa14 fa13 fa12 fa11 fa10 fa9 fa8 read / write: r/w r/w r/ w r/w r/w r/w r/w r/w reset value: 0 0 0 0 0 0 0 0 fa15 ~ fa8: flash address-high for isp function isp flash address-low register(ispfal,$f5) bit-7 bit-0 fa7 fa6 fa5 fa4 fa3 fa2 fa1 fa0 read / write: r/w r/w r/ w r/w r/w r/w r/w r/w reset value: 0 0 0 0 0 0 0 0 fa7 ~ fa0: flash address-low for isp function the ispfah & ispfal provide the 16-bit flash memory add ress for isp function. the flash memory address should not include the isp service program space address. if the flash memory address indicated by ispfah & ispfal registers overlay with the isp servic e program space address, the flash prog ram/page erase of isp function executed thereafter will have no effect.
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 11 isp flash data register (ispfd, $f6) bit-7 bit-0 fd7 fd6 fd5 fd4 fd3 fd2 fd1 fd0 read / write: r/w r/w r/ w r/w r/w r/w r/w r/w reset value: 0 0 0 0 0 0 0 0 fd7 ~fd0 : flash data for isp function the ispfd provide the 8-bit data for isp function isp flash control register (ispc, $f7) bit-7 bit-0 start unused unused unused unused unused ispf1 ispf0 read / write: r/w - - - - - r/w r/w reset value: 0 * * * * * 0 0 f[1: 0]: isp function select bit start: isp function start bit = 1: start isp function which indicated by bit 1, bit 0 (f1, f0) = 0: no operation the start bit is read-only by default, software must write thr ee specific values 55h, aah and 55h sequentially to the ispfd register to enable the start bit write attribute. that is: mov ispfd, #55h mov ispfd, #0aah mov ispfd, #55h any attempt to set start bit will not be allowed without the procedure above. after start bit set to 1 then the sm5964 hardware circ uit will latch address and dat a bus and hold the program counter until the start bit reset to 0 when isp function fini shed. user does not need to check start bit status by software method. f[1:0] isp function 00 byte program 01 chip protect 10 page erase 11 chip erase f[1:0]: isp function select bit one page of flash memory is 512 byte.
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 12 to perform byte program/page erase isp function, user nee d to specify flash address at first. when performing page erase function, sm5964 will erase entire page which flash addr ess indicated by ispfah & ispfal registers located within the page. e.g. flash address: $xymn page erase function will erase from $xy00 to $x(y+1)ff (y:even number), or page erase function will erase from $x(y-1) 00 to $xyff (y:odd number) to perform the chip erase isp function, sm5964 will erase all the flash program memory except the isp service program space, also, sm5964 w ill un-protect the flash memory automatically. to perform chip protect isp function, the sm5964 flash memory content will be read #00h. e.g. isp service program to do the byte prog ram - to program #22h to the address $1005h mov sconf,#04h ; enable sm5964 isp function mov ispfah,#10h ; set flash address-high, 10h mov ispfal,#05h ; set flash address-low, 05h mov ispfd,#22h ; set flash data to be programmed, data = 22h mov ispc,#80h ; start to program #22h to the flash address $1005h ; after byte program finis hed, start bit of ispc will be reset to 0 automatically ; program counter then point to the next instruction isp registers - system control register (sconf,$bf) bit-7 bit-0 wdr unused unused unus ed unused ispe ome alei read / write: r/w - - - - r/w r/w r/w reset value: 0 * * * * 0 1 0 the bit 2 (ispe) of sconf is isp enabl e bit. user can enable overall sm5964 isp function by setting ispe bit to 1, to disable overall isp function by set ispe to 0. the function of ispe behaves like a security key. user can di sable overall isp function to prevent software program be erased accidentally. 4. watch dog timer the watch dog timer (wdt) is a 16-bit free-running counter t hat generate reset signal if the counter overflows. the wdt is useful for systems which are su sceptible to noise, power glitches, or electronics discharge which causing software dead loop or runaway. the wdt function can help user software recover form abnormal software condition. the wdt is different from timer0, timer1 and timer2 of general 8052. to prevent a wdt reset can be done by software periodically clearing the wdt counter. user should check wdr bit of sconf register whenever un-predicted reset happened the wdt has selectable divider input for the time base source cl ock. to select the divider input, the setting of bit2~bit0 (ps2~ps0) of watch dog timer control regi ster (wdtc) should be set accordingly. to enable the wdt is done by setting 1 to the bit 7 (wdte) of wdtc. after wdte set to 1, the 16-bit counter starts to count with the selected time base source clock which se t by ps2~ps0. it will generate a reset signal when overflows. the wdte bit will be cleared to 0 automatically when sm 5964 been reset, either hardware reset or wdt reset. to reset the wdt is done by setting 1 to the clear bit of wdtc. this will clea r the content of the 16-bit counter and let the counter re-start to count from the beginning.
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 13 4.1 watch dog timer regi sters: wdtc and sconf watch dog timer registers - wdt control register (wdtc, $9f) bit-7 bit-0 wdte reserved** clear unused unused ps2 ps1 ps0 read / write: r/w - r/w - - r/w r/w r/w reset value: 0 * 0 * * 0 0 0 ** keep to ?0? when write wdtc (9fh). wdte : watch dog timer enable bit clear : watch dog timer reset bit ps[2:0] : overflow period select bits ps [2:0] divider(osc in) time period (ms) @ 40 mhz 000 8 13.12.048 001 16 26.21 010 32 52.42 011 64 104.8 100 128 209.71 101 256 419.43 110 512 838.86 111 1024 1677.72 watch dog timer register - system control register (sconf, $bf) bit-7 bit-0 wdr unused unused unus ed unused ispe ome alei read / write: r/w - - - - r/w r/w r/w reset value: 0 * * * * 0 1 0 the bit 7 (wdr) of sconf is watch dog timer reset bi t. it will be set to 1 when reset signal generated by wdt overflow. user should check wdr bit whenever un-predicted reset happened.
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 14 5. reduce emi function the sm5964 allows user to reduce the emi emission by setti ng 1 to the bit 0 (alei) of sconf register. this function will inhibit the clock signal in fosc/6hz output to the ale pin. 6. specific pulse widt h modulation (spwm) the specific pulse width modulation (spwm) module has five 8-bit channels, each channel contains a 8-bit wide spwm data register (spwmd) to decide number of continuous pulses within a spwm frame cycle. 6.1 spwm function description: each 8-bit spwm channel is composed of an 8-bit regist er which contains a 5-bit spwm in msb portion and a 3-bit binary rate multiplier (brm) in lsb portion. the value prog rammed in the 5-bit spwm port ion will determine the pulse length of the output. the 3-bit brm portion will generate and insert certain narrow pulses among an 8-spwm-cycle frame. the number of pulses generated is equal to the num ber programmed in the 3-bit brm portion. the usage of the brm is to generate equivalent 8-bit resolution spwm type dac with reasonably high repetition rate through 5-bit spwm clock speed. the pdiv[1:0] settings of spwmc ($a3 ) register are dividend of fosc to be spwm clock, fosc/2^(pdiv[1:0]+1). the spwm output cycle frame repetition rate (frequency) equals (spwm clock)/32 which is [fosc/2^(pdiv[1:0]+1)]/32. 6.2 spwm registers - p1co n, spwmc, spwmr[4:0] spwm registers - port1 configur ation register (p1con, $9b) bit-7 bit-0 spwm4e spwm3e spwm2e spwm1e spw m0e unused unused unused read / write: r/w r/w r/w r/w r/w - - - reset value: 0 0 0 0 0 * * * spwm[4:0]e :when the bit set to one, the corresponding spwm pi n is active as spwm function. when the bit reset to zero, the corresponding spwm pin is active as i/o pin. five bits are cleared upon reset. spwm registers -spwm control register (spwmc, $a3) bit-7 bit-0 unused unused unused unused unused unused pdiv1 pdiv0 read / write: - - - - - - r/w r/w reset value: * * * * * * 0 0 pdiv[1:0] : these two bits is 2?s power paramete r to form a frequency divider for input clock.
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 15 pdiv1 pdiv0 divider spwm clock, fo sc=20mhz spwm clock, fosc=24mhz 0 0 2 10mhz 12mhz 0 1 4 5mhz 6mhz 1 0 8 2.5mhz 3mhz 1 1 16 1.25mhz 1.5mhz spwm data register (spwmd[4:0], $ac, $a7 ~$a4) bit-7 bit-0 spwmd [4:0]4 spwmd [4:0]3 spwmd [4:0]2 spwmd [4:0]1 spwmd [4:0]0 brm [2:0]2 brm [2:0]1 brm [2:0]0 read / write: r/w r/w r/ w r/w r/w r/w r/w r/w reset value: 0 0 0 0 0 0 0 0 spwmd[4:0][4:0]: content of spwm da ta register. it determines duty cycle of spwm output waveform. brm[4:0][2:0]: will insert certain narrow pulses amo ng an 8-spwm-cycle frame . n = brm[4:0][2:0] number of spwm cycles inserted in an 8-cycle frame xx1 1 x1x 2 1xx 4 example of spwm timing diagram: mov spwmd0 , #83h ; spwmd0[4:0]=10h (=16t high, 16t low), brm[2:0] = 3 mov p1con , #08h ; enable p1.3 as spwm output pin (narrow pulse inserted by brm0 [2:0] setting, here brm0[2:0]=3) spwm clock = 1 / t = fosc / 2^(pdiv +1) the spwm output cycle frame frequency = spw m clock / 32 = [fosc/2^(spfs[1:0]+1)]/32 if user use fosc=20mhz, spfs[1:0] of spwmc=#03h, then spwm clock = 20mhz/2^4 = 20mhz/16 = 1.25mhz spwm output cycle frame frequenc y = (20mhz/2^4)/32=39.1khz
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 16 operating conditions symbol description min. typ. max. unit. remarks ta operating temperature -40 25 85 ambient temperature under bias vcc5 supply voltage 4.5 5.0 5.5 v fosc 25 oscillator frequency 3.0 25 25 mhz for 5v application fosc 40 oscillator frequency 3.0 40 40 mhz for 5v application dc characteristics (ta = -40 degree c to 85 degree c, vcc = 5.5v) symbol parameter valid min. max. unit test conditions vil1 input low voltage port 0,1,2,3,4,#ea -0.5 0.8 v vcc=5v vil2 input low voltage res, xtal1 00.8 v vih1 input high volt age port 0,1,2,3,4,#ea 2.0 vcc+0.5 v vih2 input high voltage res, xtal1 70%vcc vcc+0.5 v vol1 output low voltage port 0, ale, #psen 0.45 v iol=3.2ma vol2 output low vo ltage port 1,2,3,4 0.45 v iol=1.6ma 2.4 v ioh=-800ua voh1 output high voltage port 0 90%vcc v ioh=-80ua 2.4 v ioh=-60ua voh2 output high voltag e port 1,2,3,4,ale,#psen 90%vcc v ioh=-10ua iil logical 0 input current port 1,2,3,4 -75 ua vin=0.45v itl logical transition current port 1,2,3,4 -650 ua vin=2.0v ili input leakage current port 0, #ea 10 ua 0.45v syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 17 ac characteristics (16/25/40mhz, operating conditions; cl for port 0, al e and psen outputs=150pf; cl for all other output=80pf) fosc=16mhz variable fosc symbol parameter valid cycle min. t yp . max min. t yp . max unit remarks t lhll ale p ulse width rd/wrt 115 2xt - 10 ns t avll address valid to ale lo w rd/wrt 43 t - 20 ns t lla x address hold after ale lo w rd/wrt 53 t - 10 ns t lliv ale low to valid instruction in rd 240 4xt-10 ns t llpl ale low to #psen lo w rd 53 t - 10 ns t plph #psen p ulse width rd 173 3xt - 15 ns t pliv #psen low to valid instruction in rd 177 3xt-10 ns t pxi x instruction hold after #psen rd 0 0 ns t pxiz instruction float after #psen rd 87 t + 25 ns t aviv address to valid instruction in rd 292 5xt -20 ns t plaz #psen low to address float rd 10 10 ns t rlrh #rd p ulse width rd 365 6xt - 10 ns t wlwh #wr p ulse width wrt 365 6xt - 10 ns t rldv #rd low to valid data in rd 302 5xt - 10 ns t rhd x data hold after #rd rd 0 0 ns t rhdz data float after #rd rd 145 2xt+20 ns t lldv ale low to valid data in rd 590 8xt - 10 ns t avdv address to valid data in rd 542 9xt - 20 ns t llyl ale low to #wr hi g h or #rd lo w rd/wrt 178 197 3xt-10 3xt+10 ns t avyl address valid to #wr or #rd lo w rd/wrt 230 4xt-20 ns t qvwh data valid to #wr hi g h wrt 403 7xt-35 ns t qvw x data valid to #wr transition wrt 38 t - 25 ns t whq x data hold after #wr wrt 73 t + 10 ns t rlaz #rd low to address float rd 5 ns t yalh #wr or #rd hi g h to ale hi g h rd/wrt 53 72 t -10 t + 10 ns t chcl clock fall time ns t clc x clock low time ns
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 18 t clch clock rise time ns t chc x clock hi g h time ns t, tclcl clock p eriod 63 1/fosc ns isp test conditions (40 mhz, typical operating conditions, valid for sm5964 series) symbol max remark chip erase 3000ms vcc = 5v page erase 10ms ? program 30us ? protect 400us ? application reference valid for sm5964 x'tal 3mhz 6mhz 9mhz 12mhz c1 30 pf 30 pf 30 pf 30 pf c2 30 pf 30 pf 30 pf 30 pf r open open open open x'tal 16mhz 25mhz 33mhz 40mhz c1 30 pf 15 pf 5 pf 2 pf c2 30 pf 15 pf 5 pf 2 pf r open 62k ? 6.8k ? 4.7k ? note: oscillation circuit may differs with different crystal or ceramic resonator in higher oscillation frequency which was due to each crystal or ceramic resonator has its own characteristics. user should check with the crystal or ceramic resonator manufacture for appropriate value of external components. please see sm59264 application note for details.
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 19 data memory read cycle timing program memory read cycle timing
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 20 data memory write cycle timing i/o ports timing
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 21 timing critical, requirement of external clock (vss=0.0v is assumed) tm.i external program memory read cycle tm.ii external data memory read cycle
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 22 tm.iii external data memory write cycle
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 23 pdip 40l (600mil) package informatio n note: 1. refer to jedec std.ms-011(ac). 2. dimension d and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d and e1 are maximum plastic body size dimension include mold mismatch. 3. dimension b3 does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b3 dimension by more than 0.2mm . dimension in mm dimension in mil symbol min nom max min nom max a1 0.254 10 a2 3.683 3.810 3.937 145 150 155 b 0.356 0.500 0.660 14 20 26 b1 0.356 0.457 0.508 14 18 22 b2 1.016 1.270 1.524 40 50 60 b3 1.016 1.321 1.626 40 52 64 c 0.203 0.254 0.432 8 10 17 c1 0.203 0.254 0.356 8 10 14 d 52.07 52.2 52.32 2050 2055 2060 e 14.99 15.24 15.49 590 600 610 e1 13.69 13.87 13.94 539 546 549 e 2.540 100 eb 15.75 16.26 16.76 620 640 660 l 2.921 3.302 3.683 115 130 145 s 1.727 1.981 2.235 68 78 88 q1 1.651 1.778 1.905 65 70 75 0 10 0 10
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 24 plcc 44l package informatio n unit symbol inch(ref) mm(base) a 0.180(max) 4.572(max) a1 0.024 0.005 0.52 0.14 a2 0.105 0.005 2.667 0.127 b 0.018 + 0.004 - 0.002 0.457 + 0.102 - 0.051 b1 0.028 + 0.004 - 0.002 0.711 + 0.102 - 0.051 c 0.010(typ) 0.254(typ) d 0.690 0.010 17.526 0.254 d1 0.653 0.003 16.586 0.076 d2 0.610 0.020 15.494 0.508 e 0.690 0.010 17.526 0.254 e1 0.653 0.003 16.586 0.076 e2 0.610 0.010 15.494 0.254 e 0.050(typ) 1.270(typ) y 0.003(max) 0.076(max) 0~5 0~5
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 25 qfp 44l(10x10x2.0mm) package information note: 1. refer to jedc std.ms-022(ab). 2. dimension e1 do not include mold protrusion. allowable protrusion is 0.25mm per side.e1 are maximum plastic body size dimension include mold mismatch . 3. dimension b does not include dambar protrusion .allowable dambar protrusion shall not cause the lead width to exceed the maximum b3 dimension by more than 0.1 mm. dimension in mm dimension in mil symbol min nom max min nom max a 2.45 964 a1 0.05 0.15 0.25 2.1 6.0 9.6 a2 1.90 2.00 2.10 74.8 78.7 82.7 b 0.29 0.32 0.45 11.4 12.6 17.7 b1 0.29 0.30 0.41 11.4 11.8 16.1 c 0.11 0.17 0.23 4.3 6.7 9.1 c1 0.11 0.15 0.19 4.3 5.9 7.5 e 13.00 13.20 13.40 512 520 528 e1 9.90 10.00 10.10 390 394 398 e 0.800 31.5 l 0.73 0.88 1.03 28.7 34.6 40.6 l1 1.50 1.60 1.70 59.1 63.0 66.9 y 0.076 3 0 7 0 7
syncmos technologies intern ational, inc. sm5964 8-bits micro-controller 64kb isp flash & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.2 sm5964 08/2006 26 e mcu writer list company contact info programmer model number advantech 7f, no.98, ming-chung rd., shin-tien city, taipei, taiwan, roc web site: http://www.aec.com.tw tel:02-22182325 fax:02-22182435 e-mail: aecwebmaster@advantech.com.tw lab tool - 48xp (1 * 1) lab tool - 848 (1*8) hi-lo 4f, no. 20, 22, ln, 76, rui guang rd., nei hu, taipei, taiwan, roc. web site: http://www.hilosystems.com.tw tel:02-87923301 fax:02-87923285 e-mail: support@hilosystems.com.tw all - 11 (1*1) gang - 08 (1*8) leap 6th f1-4, lane 609, chunghsin rd., sec. 5, sanchung, taipei hsien, taiwan, roc web site: http://www.leap.com.tw tel:02-29991860 fax:02-29990015 e-mail: service@leap.com.tw leap-48 (1*1) su - 2000 (1*8) xeltek electronic co., ltd 338 hongwu road, nanjing, china 210002 web site: http://www.xeltek-cn.com tel:+86-25-84408399, 84543153-206 e-mail: xelclw@jlonline.com, xelgbw@jlonline.com superpro/2000 (1*1) superpro/280u (1*1) superpro/l+(1*1)

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